Position: Senior Analog/Mixed-Signal Design Engineer
What You'll Do :-
As a Senior Analog/Mixed-Signal Design Engineer, you will take a lead role in the design and development of high-performance analog and mixed-signal integrated circuits, with a strong emphasis on high-speed and high-resolution data converters. You will independently own key design blocks, drive performance optimization, collaborate closely with layout, verification, and system teams, and contribute to silicon bring-up and product maturation.
Your Responsibilities :-
Lead the design, simulation, and implementation of analog/mixed-signal circuit blocks.
Contribute to high-speed ADC architecture evaluation, performance modeling, and design trade-off analysis.
Work closely with layout engineers to guide layout floorplan, matching strategy, and parasitic-aware optimization.
Perform transistor-level simulations, corner/Monte-Carlo analysis, stability/noise/jitter analysis, and document detailed design results.
Support silicon bring-up, debug performance issues, and collaborate on validation and characterization.
Improve internal design methodologies, modeling flows, and reusable IP libraries.
What We’re Looking For :-
Master’s degree in Electrical/Electronics Engineering with 5+ years and Ph.D. with 2+ years of relevant industry experience.
Strong knowledge of analog and mixed-signal design fundamentals (noise, matching, dynamic range, stability, clocking, device physics, etc.).
Proven hands-on experience with high-speed (>10 GS/s) or high-resolution (>14-bit) ADC/DAC development.
Proficiency with Cadence/Spectre or equivalent SPICE simulation environments.
Experience working with layout teams and understanding layout-dependent effects and parasitics.
Strong problem-solving, analytical debugging skills, and ability to own designs independently.
Excellent communication skills and ability to collaborate in a team-based environment.
Nice to Have :-
Experience in post-silicon validation and lab debug.
Scripting skills (Python/Matlab) and data analysis.
Experience with advanced CMOS nodes.